Embedded_System/ARM_Core
ARM Cortex Barrier instructions
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0179b/ar01s02s04.html Barrier instructions The Cortex-M3 supports a number of barrier instructions. These can be used to ensure the completion of certain events before starting the next instruction or event. The Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor, so that all instructions following the ISB..
2012. 4. 20.
