ARM Cortex Barrier instructions

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Barrier instructions

The Cortex-M3 supports a number of barrier instructions. These can be used to ensure the completion of certain events before starting the next instruction or event.

The Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that changes to the system, for example the MPU, take immediate effect.

→ 명령어 동기화 배리어 : 새로운 명령어가 수행되기 전에 파이프라인을 플러시하고 모든 이전 명령어들이 완료되었는지를 확인한다.

The Data Synchronization Barrier (DSB) acts as a special kind of memory barrier. The DSB operation will complete when all explicit memory accesses before this instruction have completed. No instructions after the DSB will be executed until the DSB instruction has completed, that is, when all of the pending accesses have completed.

→ 데이터 동기화 배리어 : 새로운 명령어가 수행되기 전에 모든 메모리 접근이 완료되었는지를 확인한다.

The Data Memory Barrier (DMB) acts as a memory barrier. It has slightly different behavior to DSB. The DMB instruction will ensure that any memory accesses before the DMB have completed before any memory access from instructions following the DMB instruction are performed.

→ 데이터 메모리 배리어 : 새로운 메모리 접근이 수행되기 전에 모든 메모리 접근이 완료되었는지를 확인한다.

Example 8 shows a fragment of typical MPU code to show how these barrier instructions are used. This involves creating small functions using the embedded assembler, each containing a single barrier instruction. These functions can later be inlined by the linker.

Example 8. Demonstration of barrier instructions using pseudo-intrinsics

/* pseudo_intrinsics.c */
/* Small embedded assembly functions for barrier instructions*/
/* Link with armlink --inline ... */

__asm void __ISB(void){    ISB    BX lr}__asm void __DSB(void){    DSB    BX lr}/* scs.c - Initialize System Control Space registers */void SCS_init(void){    /* Code to configure the MPU regions inserted here    …    */
    /* Enable the MPU */    SCS.MPU.Ctrl |= 1;

    /* Force Memory Writes before continuing */    __DSB();
    /* Flush and refill pipline with updated permissions */    __ISB();}